The complexity of today's ICs and of the processes used to fabricate them requires constant monitoring and quality assurance to ensure that the ICs fabricated work and will continue to work over their expected lifetime. Any IC fabrication process produces a percentage of ICs that do not function due to environmental contamination, flaws in materials, mask mis-alignment, etc. Any IC fabrication process also produces a percentage of ICs that initially do function properly, but fail after only a short period of operation. This is due to, for example a metal wire within the IC that is too irregular or too thin to repeatedly carry electrical current without damaging effects such as electron migration or localized heating. When such early failures occur during actual use of an IC in a system, they can be very expensive both in terms of user satisfaction and in terms of time and cost to replace the IC in the system.
One technique that is commonly used to reduce such "infant mortality" is to subject ICs to age-accelerating stress prior to assembling them into systems. This usually involves heat and operating voltages that are higher than normal, and may involve high humidity to stimulate corrosion. After a burn-in period of perhaps an hour, the ICs are tested. Any that no longer operate properly are discarded. Thus, if an IC is going to fail early, it is likely to be caught early and inexpensively.
The technique of subjecting ICs to age-accelerating stress can also be used to estimate the expected longevity of a batch of ICs. If a statistically significant sample of ICs from a particular manufacturing run or batch is subjected to age-accelerating stress for a longer period, perhaps 100 hours, then the longevity of the ICs in that batch can be estimated. If even a few percent of the sample no fail with aging, then the batch may be seriously flawed. Commercial ICs may be expected to have failure rates of less than several hundred failures per million ICs over a several-year lifetime.
One commonly used method of subjecting ICs to age-accelerating stress is to place the ICs within a static burn-in system. Such a system comprises: (1) a burn-in chamber that subjects its contents to carefully controlled heat and humidity; (2) circuit boards that hold the ICs within the chamber; (3) a power and clock generator, located outside the burn-in chamber, that produces power and clock signals for the ICs; and (4) wires and connectors that transfer the power and the clock signals from the power and clock generator to the circuit boards and then to the power and clock pins of the ICs. The ICs are usually powered at a stress voltage, i.e. one that is somewhat higher than normal. In a static burn-in oven, the input pins of the ICs are not given any input stimuli.
A significant problem with such a static burn-in system is that, in practice, few of the electrical circuit nodes of a complex IC toggle under these conditions, i.e. without the input pins toggling state as they would when the IC is actually operated. In order to accelerate aging of a Complementary Metal-Oxide Silicon (CMOS) IC, which is the most widely used technology for commercial ICs, it is necessary to have most or all of the circuit nodes within it toggle during the burn-in period. The transistors in a CMOS IC draw only a minimal leakage current when they are steadily on or steadily off, but draw significant current during each transition from on to off or visa versa. During the operating life of an IC, it is the current traveling through a transistor, a wire or other circuit element that is likely to destroy it.
Another prior-art approach of subjecting ICs to age-accelerating stress uses dynamic burn-in systems, which do stimulate the input pins of the ICs. A dynamic burn-in system includes the above-described components of a static burn-in system but adds: (1) an input-stimuli generator, located outside of the burn-in chamber, that generates input stimuli; and (2) wires and connectors that transfer the input stimuli from the external generator to the circuit boards and then to the input pins of the ICs being exercised. The input-stimuli generator produces a programmable input-stimuli sequence. Proper design of this input-stimuli sequence can guarantee that a high percentage of the electrical nodes within the IC toggle during burn-in.
Dynamic burn-in systems are commercially available, but at a substantial premium in price over static burn-in ovens. The input signals must travel along wires and connectors that are of significant length and that go through a temperature gradient. Inductive and capacitive effects within these wires and connectors can produce cross talk among signals and distorted input-stimuli wave forms at the input pins of the ICs being exercised. Further, the input stimuli generator must be able to drive an unusually large load of input pins because it is desirable to burn-in a batch of tens or even hundreds of ICs within the same burn-in chamber.
Engineering solutions are known that produce acceptable input-stimuli wave forms, but they require considerable complexity. Unfortunately, with complexity comes not only substantial additional costs to build such dynamic burn-in systems, but also numerous added points of potential failure. Very large costs can be incurred if a burn-in system fails part way through a one-hundred-hour burn-in run--the ICs being exercised may be of questionable value for meaningful measurements.
Thus there is a need for a cost-effective, simple and reliable way to exercise a high percentage of the nodes of ICs while subjecting them to age-accelerating stress.